View RT9244_4099937.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

RT9244
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
The RT9244 is a multi-phase buck DC/DC controller integrated with all control functions for GHz CPU VRM. The RT9244 controls 2, 3 or 4 buck switching stages operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9244 controls both voltage and current loops to achieve good regulation, response & power stage thermal balance. Precise current loop using RDS(ON) as sense component builds precise load line for strict VRM DC & transient specification and also ensures thermal balance of different power stages. The settings of current sense, droop tuning, V CORE initial offset and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The DAC output of RT9244 supports K8 CPU by 5-bit VID input, precise initial value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system.
Features
Multi-Phase Power Conversion with Automatic Phase Selection K8 DAC Output with Active Droop Compens-ation for Fast Load Transient Smooth VCORE Transition at VID Jump Power Stage Thermal Balance by RDS(ON) Current Sense Hiccup Mode Over-Current Protection Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and Soft-Start High Ripple Frequency Times Channel Number RoHS Compliant and 100% Lead (Pb)-Free
Applications
AMD(R) AthlonTM 64 and OpteronTM Processors Voltage Regulator Low Output Voltage, High Current DC-DC Converters Voltage Regulator Modules
Pin Configurations
(TOP VIEW)
SS OVP VID4 VID3 VID2 VID1 VID0 VOSS COMP FB ADJ VDIF VSEN SGND ISN4 ISN3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DVD RT PGOOD PWM4 ISP4 ISP1 PWM1 PWM2 GND ISP2 ISP3 PWM3 VCC SS2 ISN1 ISN2
Ordering Information
RT9244 Package Type S : SOP-32 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating. DS9244-06 March 2007
SOP-32
www.richtek.com 1
www.richtek.com 2
+12V +12V C8 4.7uF 2 BOOT PVCC PHASE LGATE GND 4 IPD06N03LA C10 0.01uF 5 Q2 R14 4.7 VCC PWM 8 IPD09N03LA 1uH UGATE 7 C5 1uF +12V 31 R5 4.7k 32 20 29 +12V R8 2k R15 10 2 BOOT UGATE PHASE 5 8 PVCC VCC PWM GND 4 LGATE 7 6 C11 1uF 3 +12V C12 1uF C13 4.7uF C14 2200uF Q3 IPD09N03LA Q4 IPD06N03LA 1uH 28 23 25 R6 12k R7 1k VCORE C21 to C25 2200uF x 5 C6 1uF 3 6 C9 2200uF +5V C7 1uF R13 10
RT9244
RT9600
1
Q1
RT9244
2 OVP PGOOD VID4 VID3 PWM4 ISP4 ISP2 PWM2 VID2 VID1 VID0 VCC DVD RT 30 3 4 5 6 7
OVP
<
PG_VCORE <
Typical Application Circuit
VID4 >
VID3 >
VID2 >
VID1 >
VID0 >
C1 0.1uF 19 SS2 VOSS ISP1 ISP3 PWM3 GND SGND VSEN ISN1 ISN2 17 R12 2k +12V 18 R11 2k C17 1uF 13 14 24 21 22 R10 2k ADJ SS FB COMP VIDF ISN4 ISN3 R4 2k 27 R9 2k PWM1 26 1
RT9600
R1 100k 8 11 1 10 9 12 15 16
C2 0.1uF
R16 4.7 C15 0.01uF
C26 to C29 2200uF x 4
R2 15K
C3
22nF
C4
33pF
+12V
R3 2.4k
C18
R17 10
2 7 6 C16 1uF 3
RT9600
BOOT PVCC VCC PWM LGATE GND 4 UGATE PHASE
1 8
Q5 IPD09N03LA Q6 5 IPD06N03LA
4.7uF
C19 2200uF 1uH R18 4.7 C20 0.01uF
DS9244-06 March 2007
RT9244
Functional Pin Description
SS (Pin 1) Connect this SS pin to GND with a capacitor to set the start time interval. Pull this pin below 1V (ramp valley of sawtooth wave in pulse width modulator) to shutdown the converter output. OVP (Pin 2) Over voltage trip output. VID4 (Pin 3), VID3 (Pin 4), VID2 (Pin 5), VID1 (Pin 6), VID0 (Pin 7) DAC voltage identification inputs for K8. These pins are internally pulled to 2.4V if left open. VOSS (Pin 8) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. COMP (Pin 9) Output of the error amplifier and input of the PWM comparator. FB (Pin 10) Inverting input of the internal error amplifier. ADJ (Pin 11) Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the load droop. VDIF (Pin 12) VCORE differential sense output.
f OSC(kHz)
to GND with a capacitor to set the rising/falling time at VID jump. VCC (Pin 20) IC power supply. Connect this pin to a 5V supply. GND (Pin 21) Ground for the IC. PWM1 (Pin 26), PWM2 (Pin 25), PWM3 (Pin 21) & PWM4 (Pin 29) PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which use 3 channels, connect PWM4 high. Two channel systems connect PWM3 and PWM4 high. ISP1 (Pin 27), ISP2 (Pin 23), ISP3 (Pin 22) & ISP4 (Pin 28) RDS(ON) current sense inputs for each individual converter channel. Tie this pin to the component's sense node. PGOOD (Pin 30) Power good open-drain output. RT (Pin 31) Switching frequency setting. Connect this pin to GND with a resistor to set the frequency.
450 400 350 300 250 200 150 100 50
Frequency vs. RRT
VSEN (Pin 13) VCORE differential sense positive input. SGND (Pin 14) VCORE differential sense negative input. ISN1 (Pin 18), ISN2 (Pin 17), ISN3 (Pin 16) & ISN4 (Pin 15) RDS(ON) current sense inputs from each individual converter channel sense component's GND node. SS2 (Pin 19) DAC O/P ramping speed control for K8. Connect this pin
DS9244-06 March 2007
0 0 10 20 30 40 50 60 70
RRT (k)
DVD (Pin 32) Programmable power UVLO detection input. Trip threshold = 2.0V at VDVD rising.
www.richtek.com 3
Power On Reset ++ PWMCP
INH
Function Block Diagram
++ OVP Trip Point ++ OCP Setting + ++ + + PWMCP
INH
PG Trip Point
Offset Currrent Source/Sink + + Current Correction
VOSS
GAP Amplifier
SGND SS Control + + +
VSEN
SUM/M
VDIF SS
FB
COMP
ADJ
GND
-
-
Buffer Amplifier
+
-
+
-
-
Error Amplifier
+
+
-
-
+
DAC + Droop
+
VID0 VID1 VID2 VID3 VID4 SS2
INH
DAC
Oscillator & Sawtooth PWM Logic & Driver
+
+
-
-
+
www.richtek.com 4
OVP PGOOD VCC DVD RT
INH
RT9244
PWM Logic & Driver
PWM1
PWM2
PWM Logic & Driver
PWM3
PWMCP
INH
PWM Logic & Driver PWMCP
PWM4
ISN1 ISP1 ISN2 ISP2 ISN3 ISP3 ISN4 ISP4
DS9244-06 March 2007
RT9244
Table 1. Output Voltage Program
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal Output Voltage DACOUT 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.200 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown
Note: (1) 0 : Connected to GND (2) 1 : Open
DS9244-06 March 2007
www.richtek.com 5
RT9244
Absolute Maximum Ratings
(Note 1) 7V GND-0.3V to VCC+0.3V 50C/W 150C 260C -65C to 150C 2kV 200V Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Package Thermal Resistance SOP-32, JA ----------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0C to 70C Junction Temperature Range --------------------------------------------------------------------------------- 0C to 125C
Electrical Characteristics
(VCC = 5V, TA = 25C, unless otherwise specified)
Parameter VCC Supply Current Nominal Supply Current Power-On Reset POR Threshold Hysteresis VDVD Threshold Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum On-Time of Each Channel RT Pin Voltage Reference and DAC DACOUT Voltage Accuracy DAC (VID0-VID4) Input Low DAC (VID0-VID4) Input High Trip (Low to High) Hysteresis
Symbol
Test Conditions
Min
Typ
Max
Units
ICC VCCRTH VCCHYS VDVDTP VDVDHYS fOSC fOSC_ADJ VOSC VRV VRT
PWM 1,2,3,4 Open
--
12 4.2 0.5 2.0 50 200 -1.9 1.0 66 0.60 -----
-4.5 ---230 400 --75 0.65 +1 +10 0.8 --
mA V V V mV kHz kHz V V % V % mV V V
VCC Rising Enable
4.0 0.2 --170 50 --62 0.55 -1 -10 -2.0
RRT = 12k RRT = 12k
R RT = 12k VDAC 1V VDAC < 1V
VDAC VILDAC VIHDAC
To be continued
www.richtek.com 6 DS9244-06 March 2007
RT9244
Parameter DAC (VID0-VID4) Bias Current VOSS Pin Voltage Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Differential Sense Amplifier Input Impedance Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier ISP 1,2,3,4 Full Scale Source Current ISP 1,2,3,4 Current for OCP Protection SS Current Over-Voltage Trip (VSEN/DACOUT) OVP Voltage Power Good Lower Threshold (VSEN/DACOUT) Output Low Voltage VPGOOD- IPGOODL VSEN Rising IPGOOD = 4mA --92 --0.2 % V ISS OVT VOVP IOVP = 4mA VSS = 1V ---13 140 ---0.2 A % V IISPFSS IISPOCP 60 --80 --A A ZIMP GBW SR ---16 10 3 ---k MHz V/s GBW SR COMP = 10pF ---85 10 3 ---dB MHz V/s Symbol IBIAS_DAC VVOSS RVOSS = 100k Test Conditions Min 30 0.95 Typ 60 1.0 Max 90 1.05 Units A V
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions.
DS9244-06 March 2007
www.richtek.com 7
RT9244
Typical Operating Characteristics
250
GM
Adjustable Frequency
500
R1 = 3k
200
400
150
F OSC (kHz)
120
VADJ (mV)
GM1 GM3 GM4 GM2
300
100
200
50
100
0 0 20 40 60 80 100
0 0 10 20 30 40 50 60
VDS (mV)
RRT (k) (kohm)
Offset Voltage
35 30
Current Sharing at IOUT = 60A
Dropout Voltage (mV)
25 20 15 10 5 0 0 20 40 60 80 100 120
Inductor Current
(5A/Div)
PWM
(1V/Div)
Ross (kohm)
Time (2.5s/Div)
Start-up @IOUT = 60A
VSS VOUT VOUT
(1V/Div) (5V/Div)
Power Off @IOUT = 60A
VSS
(5V/Div)
(1V/Div)
PGOOD PWM
(5V/Div) (5V/Div)
PGOOD
(5V/Div)
PWM
(5V/Div)
Time (10ms/Div)
Time (100s/Div)
www.richtek.com 8
DS9244-06 March 2007
RT9244
Application Information
RT9244 is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of RT9244 and its companion MOSFET driver provides high quality CPU power and all protection functions to meet the requirement of modern VRM. Voltage Control RT9244 senses the CPU VCORE by an precise instrumental amplifier to minimize the voltage drop on PCB trace at heavy load. VSEN & SGND are the differential inputs. VDIF is the output node of the differential voltage & the input for PGOOD & OVP sense. The internal high accuracy VID DAC provides the reference voltage for K8 compliance. Control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. Like conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal VC of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Balance RT9244 senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals and then produces the balancing signals injected to pulse width modulator. If the current of some power channel is greater than average, the balancing signal reduces the output pulse width to keep the balance. Load Droop The sensed power channel current signals regulate the reference of DAC to form a output voltage droop proportional to the load current. The droop or so-called "active voltage positioning" can reduce the output voltage ripple at load transient and the LC filter size. Fault Detection The chip detects VCORE for over voltage and power good detection. The "hiccup mode" operation of over-current protection is adopted to reduce the short circuit current. The inrush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. Phase Setting and Converter Start Up RT9244 interfaces with companion MOSFET drivers (like RT9600, RT9602 series) for correct converter initialization. The tri-state PWM output (high, low and high impedance) pins sense the interface voltage at IC POR period (both VCC and DVD trip). The channel is enabled if the pin voltage is 1.2V less than VCC. Please tie the PWM output to VCC and the current sense pins to GND or left floating if the channel is unused. For 3-Channel application, connect PWM4 high. Current Sensing Setting RT9244 senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal circuit (see Figure 1).
IX
IBP
Sample & Hold Current Balance Droop Tune
GM +
IBN
ISPx ISNx
RSP1 RS RSN1 IL
< < <
Over-Current Detection
Figure 1. Current Sense Circuit
DS9244-06 March 2007
www.richtek.com 9
RT9244
I L x RS by local feedback. RSP RSP = RSN to cancel the voltage drop caused by GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off (See Figure 2). Therefore, The sensing circuit gets IX = Protection and SS Function For OVP, the RT9244 detects the VCORE by VDIF pin voltage of the differential amplifier output. Eliminate the delay due to compensation network (compared to sensing FB voltage) for fast and accurate detection. The trip point of OVP is 140% of normal output level. The PWM outputs are pulled low to turn on the low side MOSFET and turn off the high side MOSFET of the synchronous rectifier at OVP. The OVP latch can only be reset by VCC or DVD restart power on reset sequence. The PGOOD detection trip point of VCORE is 92% lower than the normal level. The PGOOD open drain output pulls low when VCORE is lower than the trip point. For VID jumping issue, only power fail conditions (VCC & DVD are lower than trip point or OVP) reset the output low. Soft-start circuit generates a ramp voltage by charging external capacitor with 13A current after IC POR acts. The PWM pulse width and VCORE are clamped by the rising ramp to reduce the inrush current and protect the power devices. Over-current protection trip point is internally set at around 100A for each channel. OCP is triggered if one channel S/H current signal IX >
I X (S/H) = T OFF
I L (S/H) x R S V O T OFF x , I L (S/H) = I L (AVG) - , R SP L 2 V IN - V O = x 5uS for fosc = 200kHz V IN V IN - V O VO - x 5uS RS V IN x = I L(AVG) - 2L R SP Falling Slope = Vo/L IL
IL(AVG)
Inductor Current
I X (S/H)
IL(S/H)
PWM Signal & High Side MOSFET Gate Signal
Low Side MOSFET Gate Signal
Figure 2. Inductor Current and PWM Signal DAC Offset Voltage & Droop Tuning The DAC offset voltage is set by compensation network 1V R f 1 & VOSS pin external resistors by R VOSS x 4 . The S/H current signals from power channels are injected to ADJ pin to create droop voltage. VADJ = RADJx 2 IX
PWM output latched at high impedance to turn off both high and low side MOSFETs in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 13A current after it is less than 90% VCC. The converter restarts after SS pin voltage < 0.2V. Three times of OCP disable the converter and only release the latch by POR acts (see Figure 4).
S.S VCORE 0V
0 .6 V x 1 .5 . Controller forces 9K
The DAC output voltage decreases by VADJ to form the VCORE load droop (see Figure 3).
VDAC VADJ 2IX1 2IX2 2IX3 2IX4 +
COUNT= 1 COUNT= 2 COUNT==33 Count = 1 Count = 2 Count
COMP Current Source IVOSS 1V = RVOSS
+ EA 1 IVOSS 4 FB RF1
Overload Applied
>
ILOAD
ADJ RADJ
VCORE
Figure 3. DAC Offset Voltage & Droop Tune Circuit
www.richtek.com 10
-
RVOSS
+
>
VOSS
0A
T0,T1
T2 TIME
T3,T4
>
Figure 4.
DS9244-06 March 2007
RT9244
3-Phase Converter and Components Function Grouping
12V
VCC PVCC
BOOT UGATE PHASE
RT9600
PWM SGND VSEN VDIF PWM1 VID OVP PGOOD ISP1 ISN1 VCC PVCC BOOT UGATE PHASE VCORE 12V LGATE GND
RT9244
Compensation & Offset COMP FB ADJ Droop Setting 12V DVD VOSS SS,SS2 DAC Offset Voltage Setting RT Frequency Setting ISP3 ISN3 PWM3 GND ISP2 ISN2 PWM2
RT9600
PWM LGATE GND
Driver Power UVLO
12V
VCC PVCC
BOOT UGATE PHASE
RT9600
PWM LGATE GND Current Sense Components
Design Procedure Suggestion
Voltage Loop Setting a. Output filter pole and zero (Inductor, output capacitor value & ESR). b. Error amplifier compensation & sawtooth wave amplitude (compensation network). c. Kelvin sense for VCORE. Current Loop Setting a. GM amplifier S/H current (current sense component Ron, ISPx & ISNx pin external resistor value, keep ISPx current < 60A at full load condition for better load line linearity). b. Over-current protection trip point (Internal setting, keep ISPx current < 100A at OCP condition for precision issue).
DS9244-06 March 2007
VRM Load Line Setting a. Droop amplitude (ADJ pin resistor). b. No load offset (additional resistor in compensation network). c. DAC offset voltage setting (VOSS pin & compensation network resistor). Power Sequence & SS DVD pin external resistor and SS pin capacitor. PCB Layout a. Kelvin sense for current sense GM amplifier input. b. Refer to layout guide for other item.
www.richtek.com 11
RT9244
Design Example
Given:
Apply for three phase converter VIN = 12V ILOAD (MAX) = 60A VDROOP = 120mV at full load OCP trip point set at 33A for each channel (S/H) RDS(ON) = 6m of low side MOSFET at 27C L = 2H COUT = 9,000F with 2m ESR. 1. Compensation Setting a. Modulator Gain, Pole and Zero : From the following formula : V IN 12V Modulator Gain = = = 4.2 (12.46dB) V RAMP 1.9V x 3 where VRAMP : ramp amplitude of sawtooth wave LC Filter Pole = 2 x LC = 1.2kHz and ESR Zero = 2 x ESR x COUT = 8.8kHz b. EA Compensation Network : Select R1 = 2.4k, R2 = 24k, C1 = 6.6nF, C2 = 33pF and use the type 2 compensation scheme shown in Figure 5.
R2
Asymptotic Bode Plot of PWM Loop Gain
100 80 60
Uncompensated EA Gain
Gain (dB)
VCORE = 1.5V
40 20 0 -20 -40 -60 10 10 100 100 1K 1000
Compensated EA Gain PWM Loop Gain Modulator Gain
10K 10000
100K 100000
1M 10M 1000000 10000000
Frequency (Hz)
Figure 6. 2. Droop & DAC Offset Setting For each channel the load current is 60A / 3 = 20A and the ripple current, IL, is given as : 5 s x 1.5V x 1- 1.5V = 3.28A 2uH 12V IL = 18.36 A . The load current, IL, at S/H is 20 A - 2 Using the following formula to select the appropriate IX (MAX) for the S/H of GM amplifier : R DS(ON) x 18.36A I X (MAX) = R SP The suggested IX is in the order of 50 to 60A, select RSP = RSN = 2k, then IX (MAX) will be 55A. VDROOP = 120mV = 55A x 2 x 3 (phase no.) x RADJ, therefore RADJ will be 360. The RDS(ON) of MOSFET varies with temperature rise. When the low side MOSFET working at 70C and 5000ppm/C temperature coefficient of RDS(ON), the RDS(ON) at 70C is given as : 6m x {1+ (70C - 27C) x 5000ppm/C} = 7.3m. RADJ at 70C is given as : RADJ_27C x (RDS(ON)_27C / RDS(ON)_70C) = 296 3. Over-Current Protection Setting OCP trip point is internally set at around 100A of IX for each channel. As above-selected RSP = RSN = 2k, the OCP trip point is found using :
IX (OCP) = RDS(ON) x IL (TRIP) 6m x 33A = = 100 A RSP 2k
2
1
1
C1
R3 R1
C3
C2 COMP + DACOUT FB
> VDIF
R3,C3 are used in type 3 compensation scheme (left NC in type 2)
Figure 5. From the following formulas : 1 1 FZ = , FP = 2 x R 2 x C 1 C1 x C 2 2 x R 2 x R2 C1 + C 2 Middle Band Gain =
R1
By calculation, the FZ = 1kHz, FP = 200kHz and Middle Band Gain is 10 (i.e 20dB). The asymptotic bode plot of EA compensation and PWM loop gain is shown as Figure 6.
www.richtek.com 12
4. Soft-Start Capacitor Selection CSS = 0.1F is the suitable value for most application.
DS9244-06 March 2007
RT9244
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3,4 and ISN1,2,3,4 should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. 4. The compensation, bypass and other function setting components should be near the IC and away from the noisy power path.
SW1
L1
VIN RIN CIN
VOUT
COUT
RL
V
SW2 L2
Figure 7. Power Stage Ripple Current Path
DS9244-06 March 2007
www.richtek.com 13
RT9244
+12V CBP VCC PVCC PWM BOOT UGATE PHASE CIN
Kelvin Sense
Next to IC
+12V or +5V
PWM RT VOSS
VCC CBP
+5VIN
CBOOT LO1
Next to IC COMP CC
VCORE
RT9600
LGATE GND
COUT RSIP
RT9244
ISPx ISNx ADJ FB
RC Locate next to FB Pin RFB
Locate near MOSFETs
RSIN
VSEN GND
For Thermal Couple
Figure 8. Layout Consideration
www.richtek.com 14
DS9244-06 March 2007
RT9244
Outline Dimension
A H M
J
B
F
C I D
Dimensions In Millimeters Symbol Min A B C D F H I J M 0.229 0.102 10.008 0.381 20.320 7.391 2.362 0.330 1.27 0.330 0.305 10.643 1.270 Max 20.726 7.595 2.642 0.508
Dimensions In Inches Min 0.800 0.291 0.093 0.013 0.050 0.009 0.004 0.394 0.015 0.013 0.012 0.419 0.050 Max 0.816 0.299 0.104 0.020
32-Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
DS9244-06 March 2007
www.richtek.com 15

▲Up To Search▲

Price & Availability of RT9244

	To Download RT9244 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .